Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1257 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
SCKCR—System Clock Control Register H'FDE6 System
7
PSTOP
0
R/W
6
—
0
—
5
—
0
—
4
—
0
—
3
STCS
0
R/W
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
R/W
:
:
:
ø clock output disable
PSTOP High-speed mode, Sleep mode, Software standby mode, Hardware standby
medium-speed mode, subsleep mode watch mode, direct transition mode
subactive mode
0 φ output (initial value) φ output High level (fixed) High impedance
1 High level (fixed) High level (fixed) High level (fixed) High impedance
Frequency multiplier switching mode select
0 Specified multiplier valid after transferring to software standby mode,
watch mode, and subactive mode.
1 Specified multiplier valid immediately after setting value in STC bit.
System clock select 2 to 0
SCK2 SCK1 SCK0
0 0 0
1
1 0
1
1 0 0
1
1 — —
Bus master set to high-speed mode.
Medium-speed clock: φ/2
Medium-speed clock: φ/4
Medium-speed clock: φ/8
Medium-speed clock: φ/16
Medium-speed clock: φ/32