Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1261 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
LPWRCR—Low-Power Control Register H'FDEC System
7
DTON
*1
0
R/W
6
LSON
*1
0
R/W
5
NESEL
*1
0
R/W
4
SUBSTP
*1
0
R/W
3
RFCUT
*1
0
R/W
0
STC0
0
R/W
2
—
0
R/W
1
STC1
0
R/W
Direct transfer ON flag
0 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers to sleep
mode, software standby mode, or watch mode
*
.
• When the SLEEP command is executed in subactive mode, operation transfers to subsleep mode or watch mode
*
.
1 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers directly to
subactive mode
*
, or transfers to sleep mode or software standby mode.
• When the SLEEP command is executed in subactive mode
*
, operation transfers directly to high-speed mode or
transfers to subsleep mode.
Note: * Always select high-speed mode when transferring to watch mode or subactive mode.
Low-speed ON flag
0 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation
transfers to sleep mode, software standby mode, or watch mode*.
• When the SLEEP command is executed in subactive mode*, operation transfers to watch mode*, or
directly to high-speed mode.
• Operation transfers to high-speed mode after watch mode* is canceled.
1 • When the SLEEP command is executed in high-speed mode, operation transfers to watch mode* or
subactive mode.
• When the SLEEP command is executed in subactive mode*, operation transfers to subsleep mode or
watch mode*.
• Operation transfers to subactive mode immediately watch mode* is canceled.
Note: * Always select high-speed mode when transferring to watch mode or subactive mode.
A system clock frequency multiplied by the multiplication factor
(STC1 and STC0) should not exceed the maximum operating
frequency defined in sections 25, 26, and 27, Electrical
Characteristics.
Current consumption and noise can be reduced by using this
function’s PLL
×
4 setting and lowering the external clock frequency.
Note:
Noise elimination sampling frequency select
0 Sampling uses φ/32 clock.
1 Sampling uses φ/4 clock.
Subclock enable
0 Subclock generation enabled.
1 Subclock generation disabled.
Oscillator circuit feedback resistor control bit
0 Feedback resistor ON when main clock
operating; OFF when not operation.
1 Feedback resistor OFF.
Frequency multiplier
STC1 STC0 Description
0 0 × 1 (initial value)
1 × 2
1 0 × 4
1 Do not set.
Bit
Initial value
R/W
:
:
:
Bit
Initial value
R/W
:
:
:
Note: 1. The H8S/2695 has no subclock function, so only a 0 may be written to this bit.