Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1263 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
BCRA—Break Control Register A
BCRB—Break Control Register B
H'FE08
H'FE09
PBC
PBC
R/(W)*
0
CMFA
7
R/W
0
CDA
6
R/W
0
BAMRA2
5
R/W
0
BAMRA1
4
R/W
0
BAMRA0
3
R/W
0
CSELA1
2
R/W
0
CSELA0
1
R/W
0
BIEA
0
Notes: The bit configuration of BCRB is the same as that of BCRA.
* Only 0 can be written to these bits (to clear these flags).
BAMRA
0
0
1
All bits, without masking BARA, included in break condition.
BAA0 (LSB) masked and not included in break condition.
BAA1 and BAA0 (low 2 bits) masked and not included in break condition.
BAA2 to BAA0 (low 3 bits) masked and not included in break condition.
BAA3 to BAA0 (low 4 bits) masked and not included in break condition.
BAA7 to BAA0 (low 8 bits) masked and not included in break condition.
BAA11 to BAA0 (low 12 bits) masked and not included in break condition.
BAA15 to BAA0 (low 16 bits) masked and not included in break condition.
0
BAMRA
1
0
0
BAMRA
2
0
0
10
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
When the CPU is the bus master, PC break performed.
When the CPU or DTC is the bus master, PC break performed.
0
1
[Clearing condition]
Writing 0 to CMFA after reading CMFA=1.
[Setting condition]
When channel A conditions are true.
0
1
Condition match flag A
CPU cycle/DTC cycle select A
Break address mask register A2 to A0
Disables PC break interrupt.
Enables PC break interrupt.
0
1
Break interrupt enable
Break condition select
00
CSELA0
Sets instruction fetch as break condition.
Sets data read cycle as break condition.
Sets data write cycle as break condition.
Sets data read/write cycle as break condition.
CSELA1
10
01
11
Bit :
Initial value
R/W
:
: