Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1265 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
ISR—IRQ Status Register H'FE15 Interrupt Controller
7
IRQ7F
0
R/(W)*
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
0
IRQ0F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
Note: * Only 0 can be written to these bits (to clear these flags).
IRQ7 to IRQ0 flag
0
1
(n= 7 to 0)
Bit
Initial value
R/W
:
:
:
[Clearing]
(1) Writing 0 to flag IRQnF after reading IRQnF=1;
(2) When interrupt exception processing is executed when set for LOW-level detection
(IRQnSCB=IRQnSCA=0) and, in addition, the IRQn input level is HIGH;
(3) When IRQn interrupt exception processing is executed when set for rising edge or
falling edge or both rising edge and falling edge detection (IRQnSCB=1 and
IRQnSCA=1);
(4) When the DTC starts due to IRQn interrupt and the DTC MRB DISEL bit is 0.
[Setting]
(1) When the IRQn input level changes to LOW when set for LOW level detection
(IRQnSCB=IRQnSCA=0);
(2) When a falling edge occurs at the IRQn input when set for falling edge detection
(IRQnSCB=0, IRQnSCA=1);
(3) When a rising edge occurs at the IRQn input when set for rising edge detection
(IRQnSCB=1, IRQnSCA=0);
(4) When either a falling edge or rising edge occurs at the IRQn input when set for both
falling edge and rising edge detection (IRQnSCB=IRQnSCA=1).