Datasheet

Appendix B Internal I/O Register
Page 1266 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
DTCER—DTC Enable Register H'FE16
to
H'FE1E
DTC
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
0
DTCE0
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
DTC startup by interrupt disabled
[Clearing conditions]
• When data transmission ends with the DISEL bit =1.
• On completion of the specified number of transmissions.
0
1
DTC start enable
0
DTC startup by interrupt enabled
[Retention condition]
When DISEL=0 and the specified number of transmissions has not completed.
DTCEn
(n= 7 to 0)
Bit
Initial value
R/W
:
:
: