Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1267 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
DTVECR—DTC Vector Register H'FE1F DTC
7
SWDTE
0
R/(W)*
1
6
DTVEC6
0
R/(W)*
2
5
DTVEC5
0
R/(W)*
2
4
DTVEC4
0
R/(W)*
2
3
DTVEC3
0
R/(W)*
2
0
DTVEC0
0
R/(W)*
2
2
DTVEC2
0
R/(W)*
2
1
DTVEC1
0
R/(W)*
2
Notes: 1.
2.
Only 1 can be written to the SWDTE bit.
DTVEC6 to DTVEC0 can be written to when SWDTE=0.
DTC software startup enable
DTC software startup disabled
[Clearing conditions]
• When DISEL=0 and the specified number of transmissions
has not completed.
• When 0 is written after a software startup data transmit end
interrupt (SWDTEND) request is sent to the CPU.
0
1
DTC software startup vector 6 to 0
0
DTC software startup enabled
[Retention conditions]
• When DISEL=1 and data transmission ends;
• On completion of the specified number of transmissions;
• During data transmission by software startup.
Bit
Initial value
R/W
:
:
: