Datasheet
Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1279 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TCR0—Timer Control Register 0
TCR3—Timer Control Register 3
H'FF10
H'FE80
TPU0
TPU3
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Channel 0: TCR0
Channel 3: TCR3
Counter clear 2, 1, 0
Clock edge 1, 0
00 TCNT clearing disabled.
CCLR1CCLR2
TCNT cleared at TGRA compare match/input capture.
1 TCNT cleared at TGRB compare match/input capture.
0
CCLR0
1
0
01 TCNT clearing disabled.0
1
TCNT cleared at TGRC compare match/input capture.
*
2
1
TCNT cleared when other channel counters with synchronized
clearing or synchronized operation are cleared.
*
1
1 TCNT cleared at TGRD compare match/input capture.
*
2
0
1 TCNT cleared when other channel counters with synchronized
clearing or synchronized operation are cleared.
*
1
Time prescaler 2, 1, 0
TCR0
TPSC0TPSC1TPSC2
TPSC0TPSC1TPSC2
TCR3
00 Internal clock: counts on ø/1
Internal clock: counts on ø/4
1 Internal clock: counts on ø/16
0
1
0
01 External clock: counts on TCLKA pin input0
1
Internal clock: counts on ø/10241
Internal clock: counts on ø/64
1 Internal clock: counts on ø/2560
1 Internal clock: counts on ø/4096
00 Internal clock: counts on ø/1
Internal clock: counts on ø/4
1 Internal clock: counts on ø/16
0
1
0
01 External clock: counts on TCLKA pin input0
1
External clock: counts on TCLKB pin input1
Internal clock: counts on ø/64
1 External clock: counts on TCLKC pin input0
1 External clock: counts on TCLKD pin input
00 Counts on rising edge.
CKEG0CKEG1
1 Counts on falling edge.
—1 Counts on both edges.
Note: Internal clock edge selection is valid only when the input clock is ø/4 or slower. This
setting is ignored when the input clock is ø/1 or an overflow or underflow in another
channel is selected.
Bit
Initial value
R/W
:
:
:
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer
register setting has priority, and compare match/input capture does not occur.