Datasheet

Appendix B Internal I/O Register
Page 1280 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TMDR0—Timer Mode Register 0
TMDR3—Timer Mode Register 3
H'FF11
H'FE81
TPU0
TPU3
7
—
1
—
6
—
1
—
5
BFB
0
R/W
4
BFA
0
R/W
3
MD3
0
R/W
0
MD0
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
Channel 0: TMDR0
Channel 3: TMDR3
Normal TGRB operation.
Buffer operation of TGRB and TGRD.
0
1
Normal TGRA operation.
Buffer operation of TGRA and TGRC.
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase calculation mode 1
Phase calculation mode 2
Phase calculation mode 3
Phase calculation mode 4
0
1
Buffer operation B
Modes 3 to 0
Buffer operation A
0
1
0
MD0 MD1MD2
*2
0
0
1
1
001
—
1
01
1
***
MD3
*1
0
1
* : Don't care
Notes: 1.
2.
MD3 is a reserved bit. Only write 0 to this bit.
Phase calculation mode cannot be set for channels 0 and 3.
Only write 0 to MD2.
Bit
Initial value
R/W
:
:
: