Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1285 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TIOR1—Timer I/O Control Register 1 H'FF22 TPU1
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
*: Don't care
TGR1A I/O Control
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare match/
input capture
TGR1A is
output
compare
register
TGR1A is
input
capture
register
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCA1 pin
Capture input
source is TGR0A
compare match/
input capture
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
*
*: Don't care
TGR1B I/O Control
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of TGR0C
compare match/input capture
TGR1B is
output
compare
register
TGR1B is
input
capture
register
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCB1 pin
Capture input
source is TGR0C
compare match/
input capture
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
*
Bit
Initial value
R/W
:
:
: