Datasheet
Appendix B Internal I/O Register
Page 1288 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TIOR0L—Timer I/O Control Register 0L H'FF13 TPU0
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
0
IOC0
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
*: Don't care
TGR0C I/O Control
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
TGR0C is
output
compare
register*
1
TGR0C is
input
capture
register
*
1
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
*
*: Don't care
TGR0D I/O Control
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
*
1
TGR0D is
output
compare
register
*
2
TGR0D is
input
capture
register
*
2
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
*
Notes: 1.
2.
When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the
TCNT1 count clock, this setting is invalid and input capture is not generated.
When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
Note: 1.
When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
Bit
Initial value
R/W
:
:
: