Datasheet

Appendix B Internal I/O Register
Page 1290 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TSR3—Timer Status Register 3
TSR0—Timer Status Register 0
H'FE85
H'FF15
TPU3
TPU0
7
—
1
—
6
—
1
—
5
—
0
—
4
TCFV
0
R/(W)*
3
TGFD
0
R/(W)*
0
TGFA
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
Note: * Only 0 can be written to these bits (to clear these flags).
Channel 0: TSR0
Channel 3: TSR3
Input capture/output compare flag A
Overflow flag
Input capture/output compare flag B
Input capture/output compare flag C
Input capture/output compare flag D
[Clearing conditions]
(1) When the DTC is started by a TGID interrupt and the DTC MRB
DISEL bit is 0;
(2) Writing 0 to TGFD after reading TGFD=1.
[Setting conditions]
(1) When TGRD is functioning as the output compare register and
TCNT=TGRD;
(2) When TGRD is functioning as the input capture register and the value
of TCNT is sent to TGRD by the input capture signal.
0
1
[Clearing conditions]
(1) When the DTC is started by a TGIC interrupt and the DTC MRB
DISEL bit is 0;
(2) Writing 0 to TGFC after reading TGFC=1.
[Setting conditions]
(1) When TGRC is functioning as the output compare register and
TCNT=TGRC;
(2) When TGRC is functioning as the input capture register and the value
of TCNT is sent to TGRC by the input capture signal.
0
1
[Clearing conditions]
(1) When the DTC is started by a TGIB interrupt and the DTC MRB
DISEL bit is 0;
(2) Writing 0 to TGFB after reading TGFB=1.
[Setting conditions]
(1) When TGRB is functioning as the output compare register and
TCNT=TGRB;
(2) When TGRB is functioning as the input capture register and the value
of TCNT is sent to TGRB by the input capture signal.
0
1
[Clearing conditions]
(1) When the DTC is started by a TGIA interrupt and the DTC MRB
DISEL bit is 0;
(2) When the DMAC is started by a TGIA interrupt and the DMAC
DMABCR DTA bit is 1;
(3) Writing 0 to TGFA after reading TGFA=1.
[Setting conditions]
(1) When TGRA is functioning as the output compare register and
TCNT=TGRA;
(2) When TGRA is functioning as the input capture register and the value
of TCNT is sent to TGRA by the input capture signal.
0
1
[Clearing condition]
Writing 0 to TCFV after reading TCFV=1.
[Setting condition]
When the TCNT value overflows (H’FFFF → H’0000).
0
1
0
Bit
Initial value
R/W
:
:
: