Datasheet
Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1293 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TCR4—Timer Control Register 4
TCR5—Timer Control Register 5
TCR1—Timer Control Register 1
TCR2—Timer Control Register 2
H'FE90
H'FEA0
H'FF20
H'FF30
TPU4
TPU5
TPU1
TPU2
7
—
0
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Channel 1: TCR1
Channel 2: TCR2
Channel 4: TCR4
Channel 5: TCR5
Clock edge 1, 0
00 TCNT clearing disabled.
CCLR0CCLR1
0
Reserve
*
2
1 TCNT cleared at TGRA compare match/input capture.
01 TCNT cleared at TGRB compare match/input capture.
1 TCNT cleared when other channel counters with synchronized clearing
or synchronized operation are cleared.
*
1
Counter clear 2, 1, 0
00 Counts on rising edge.
CKEG0CKEG1
1 Counts on falling edge.
—1 Counts on both edges.
Note: Internal clock edge selection is valid only when the input clock is ø/4 or slower. This setting
is ignored when the input clock is ø/1 or an overflow or underflow in another channel is selected.
Notes: 1.
2.
Sync operation is selected by setting 1 in the TSYR SYNC bit.
Bit 7 of channels 1, 2, 4, and 5 is reserved. This bit always returns 0 when read, and cannot be written to.
Bit
Initial value
R/W
:
:
:
Time prescaler 2, 1, 0
TCR1
TCR2
00 Internal clock: counts on ø/1
Internal clock: counts on ø/4
1 Internal clock: counts on ø/16
0
1
0
01 External clock: counts on TCLKA pin input0
1
External clock: counts on TCLKB pin input1
Internal clock: counts on ø/64
1 External clock: counts on TCLKC pin input0
1 Internal clock: counts on ø/1024
00 Internal clock: counts on ø/1
Internal clock: counts on ø/4
1 Internal clock: counts on ø/16
0
1
0
01 External clock: counts on TCLKA pin input0
1
External clock: counts on TCLKB pin input1
Internal clock: counts on ø/64
1 Internal clock: counts on ø/2560
1 Counts on TCNT2 overflow/underflow
TCR4
Note: This setting is ignored when channel 2 is in phase counting mode.
Note: This setting is ignored when channel 1 is in phase counting mode.
TCR5
Note: This setting is ignored when channel 4 is in phase counting mode.
Note: This setting is ignored when channel 5 is in phase counting mode.
00 Internal clock: counts on ø/1
Internal clock: counts on ø/4
1 Internal clock: counts on ø/16
0
1
0
01 External clock: counts on TCLKA pin input0
1
External clock: counts on TCLKC pin input1
Internal clock: counts on ø/64
1 Internal clock: counts on ø/2560
1 External clock: counts on TCLKD pin input
00 Internal clock: counts on ø/1
Internal clock: counts on ø/4
1 Internal clock: counts on ø/16
0
1
0
01 External clock: counts on TCLKA pin input0
1
External clock: counts on TCLKC pin input1
Internal clock: counts on ø/64
1 Internal clock: counts on ø/10240
1 Counts on TCNT5 overflow/underflow