Datasheet

Appendix B Internal I/O Register
Page 1294 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TMDR4—Timer Mode Register 4
TMDR5—Timer Mode Register 5
TMDR1—Timer Mode Register 1
TMDR2—Timer Mode Register 2
H'FE91
H'FEA1
H'FF21
H'FF31
TPU4
TPU5
TPU1
TPU2
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
MD3
0
R/W
0
MD0
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase calculation mode 1
Phase calculation mode 2
Phase calculation mode 3
Phase calculation mode 4
Modes 3 to 0
0
1
0
MD0 MD1MD2
*
2
0
0
1
1
001
—
1
01
1
***
MD3
*
1
0
1
* : Don’t care
Notes: 1.
2.
MD3 is a reserved bit. Only write 0 to this bit.
Phase calculation mode cannot be set for channels 0 and 3.
Only write 0 to MD2.
Bit
Initial value
R/W
:
:
: