Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1297 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TSTR—Timer Start Register H'FEB0 TPU Common
7
—
0
—
6
—
0
—
5
CST5
0
R/W
4
CST4
0
R/W
3
CST3
0
R/W
0
CST0
0
R/W
2
CST2
0
R/W
1
CST1
0
R/W
Counter start 5 to 0
TCNTn counting operation disabled.
TCNTn counting operation enabled.
0
1
Note: When the TIOC pin is operating as an output pin, writing 0 to a CST bit
disables counting. The TIOC pins output compare output level is maintained.
When a CST bit is 0, the output level of the pin is updated to the set initial
output value by writing to TIOR.
(n= 5 to 0)
Bit
Initial value
R/W
:
:
:
TSYR—Timer Synchro Register H'FEB1 TPU Common
7
—
0
—
6
—
0
—
5
SYNC5
0
R/W
4
SYNC4
0
R/W
3
SYNC3
0
R/W
0
SYNC0
0
R/W
2
SYNC2
0
R/W
1
SYNC1
0
R/W
Bit
Initial value
R/W
:
:
:
Timer sync 5 to 0
TCNTn operate independently (TCNTs are preset and cleared
independently of other channels)
TCNTn operate in sync mode. Synchronized
TCNT presetting and clearing enabled.
0
1
(n= 5 to 0)
Note: The SYNC bit of a minimum of two channels must be set to 1 in order to
select sync operation.
To enable sync clearing, in addition to the SYNC bits, the TCR CCLR2 to
CCLR0 bits must be set for the TCNT clearing factors.