Datasheet

Appendix B Internal I/O Register
Page 1302 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
BCRH—Bus Control Register H H'FED4 Bus Controller
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
0
RMTS0
*1
0
R/W
2
RMTS2
*1
0
R/W
1
RMTS1
*1
0
R/W
No idle cycle is inserted when an external read cycle
follows an external read cycle of another area.
An idle cycle is inserted when an external read cycle
follows an external read cycle of another area. (Initial value)
0
1
0
Idle cycle insertion 1
No idle cycle is inserted when an external read cycle follows
an external write cycle.
An idle cycle is inserted when an external read cycle follows
an external write cycle. (Initial value)
1
Idle cycle insertion 0
Area 0 is basic bus interface. (Initial value)
Area 0 is burst ROM interface.
0
1
Burst ROM enable
Burst cycle = 1 state.
Burst cycle = 2 states.
0
1
Burst access = 4 words max.
Burst access = 8 words max.
0
1
Burst cycle select 1
RAM type select
Burst cycle select 0
Notes: When all areas selected in the DRAM area are set for 8-bit access, the PF2
pin can be used as an I/O port or BREQO or WAIT. When set for contiguous
DRAM the bus widths for areas 2 to 5 and the number of access states
(number of programmable waits) must be set to the same values. Do not
attempt to set combinations other than those shown in the table.
* This function is not available in the H8S/2695.
0
1
0
RMTS0 Area 2RMTS1RMTS2 Area 3 Area 4 Area 5
0
0
1
1
111
Normal area
DRAM area*Normal area
DRAM area*Normal area
DRAM area*
Contiguous DRAM area*
Bit
Initial value
R/W
:
:
:
Note: 1. In the H8S/2695 only a 0 may be written to RMTS2, RMTS1, or RMTS0.