Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1303 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
BCRL—Bus Control Register L H'FED5 Bus Controller
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
—
0
—
4
OES*
0
R/W
3
DDS*
1
R/W
0
WAITE
0
R/W
2
RCTS*
0
R/W
1
WDBE
0
R/W
Bit
Initial value
R/W
:
:
:
Release of external bus privileges disabled. BREQ,
BACK, and BREQO can be used as I/O ports.
Release of external bus privileges enabled.
0
1
Bus release enable
Wait input via WAIT pin disabled. The WAIT pin can be used as an I/O port.
Wait input via WAIT pin enabled.
0
1
WAIT pin enable
Note: * This function is not available in the H8S/2695.
BREQO output disabled. BREQO can be used as an I/O port.
BREQO output enabled.
0
1
BREQO pin enable
CS3 pin used as port or as CS3 signal output.
When only area 2 is set as DRAM, or when
areas 2 to 5 are set as contiguous DRAM space,
the CS3 pin is used as the OE pin.
0
1
OE select
Do not use write data buffer function.
Use write data buffer function.
0
1
Write data buffer enable
CAS signal output timing is the same when reading and writing.
When reading, the CAS signal is asserted one half cycle faster than
when writing.
0
1
Read CAS timing select
When performing DMAC single address transmission to the
DRAM space, always perform full access. The DACK signal
level changes to LOW from T
r
or T
1
cycle.
Burst access is also available when performing DMAC single
address transmission to the DRAM space. The DACK signal
level changes to LOW from T
C1
or T
2
cycle.
0
1
DACK timing select