Datasheet

Appendix B Internal I/O Register
Page 1304 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
MCR—Memory Control Register H'FED6 Bus Controller
(This function is not available in the H8S/2695.)
7
TPC
0
R/W
6
BE
0
R/W
5
RCDM
0
R/W
4
CW2
0
R/W
3
MXC1
0
R/W
0
RLW0
0
R/W
2
MXC0
0
R/W
1
RLW1
0
R/W
Bit
Initial value
R/W
:
:
:
One precharge cycle state inserted.
Two precharge cycle states inserted.
0
1
0
TP cycle control
Burst access disabled (permanently full access).
DRAM space accessed in high-speed page mode.
1
Burst access enable
DRAM interface: RAS up mode selected.
DRAM interface: RAS down mode selected.
0
1
RAS down mode
Insert 3 wait states.
Insert 1 wait state.
Insert 2 wait states.
Do not insert wait state.
Reserved bit
Refresh cycle wait control 1, 0
Multiplex shift count 1, 0
0
1
0
RLW0 RLW1
0
1
1
—
9-bit shift
(1) When set for 8-bit access space: Row addresses A23 to A9 are
targets of comparison.
(2) When set for 16-bit access space: Row addresses A23 to A10 are
targets of comparison.
10-bit shift
(1) When set for 8-bit access space: Row addresses A23 to A10 are
targets of comparison.
(2) When set for 16-bit access space: Row addresses A23 to A11 are
targets of comparison.
8-bit shift
(1) When set for 8-bit access space: Row addresses A23 to A8 are
targets of comparison.
(2) When set for 16-bit access space: Row addresses A23 to A9 are
targets of comparison.
0
1
0
MXC0MXC1
0
1
1