Datasheet

Appendix B Internal I/O Register
Page 1310 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
MAR1AH—Memory Address Register 1AH
MAR1AL—Memory Address Register 1AL
H'FEF0
H'FEF2
DMAC
DMAC
*: Undefined
Bit
MAR1AL
Initial value
R/W
15
*
R/W
14
*
R/W
13
*
R/W
12
*
R/W
11
*
R/W
10
*
R/W
9
*
R/W
8
*
R/W
7
*
R/W
6
*
R/W
5
*
R/W
4
*
R/W
3
*
R/W
2
*
R/W
1
*
R/W
0
*
R/W
Bit
MAR1AH
Initial value
R/W
:
:
:
:
:
:
:
:
31
—
0
—
30
—
0
—
29
—
0
—
28
—
0
—
27
—
0
—
26
—
0
—
25
—
0
—
24
—
0
—
23
*
R/W
22
*
R/W
21
*
R/W
20
*
R/W
19
*
R/W
18
*
R/W
17
*
R/W
16
*
R/W
In short address mode: Specifies transfer destination/transfer source address
In full address mode: Specifies transfer destination
ETCR1A—Transfer Count Register 1A H'FEF6 DMAC
*: Undefined
Bit
ETCR1A
Initial value
R/W
:
:
:
:
Sequential mode
Idle mode
Normal mode
Repeat mode
Block transfer mode
15
*
R/W
14
*
R/W
13
*
R/W
12
*
R/W
11
*
R/W
10
*
R/W
9
*
R/W
8
*
R/W
7
*
R/W
6
*
R/W
5
*
R/W
4
*
R/W
3
*
R/W
2
*
R/W
1
*
R/W
0
*
R/W
Transfer counter
Block size counter
Transfer counter
Holds number of transfers
Holds block size