Datasheet

Appendix B Internal I/O Register
Page 1314 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
DMAWER—DMA Write Enable Register H'FF60 DMAC
(This function is not available in the H8S/2695.)
7
—
0
—
6
—
0
—
5
—
0
—
4
—
0
—
3
WE1B
0
R/W
0
WE0A
0
R/W
2
WE1A
0
R/W
1
WE0B
0
R/W
Write enable 1A
Disables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and
DMATCR bit 5. (initial value)
Enables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and
DMATCR bit 5.
0
1
Disables writing to all DMACR1A bits, and DMABCR bits 10, 6, and 2.
(initial value)
Enables writing to all DMACR1A bits, and DMABCR bits 10, 6, and 2.
0
1
Disables writing to all DMACR0A bits, and DMABCR bits 8, 4, and 0.
(initial value)
Enables writing to all DMACR0A bits, and DMABCR bits 8, 4, and 0.
0
1
Write enable 0B
Disables writing to all DMACR0B bits, DMABCR bits 9, 5, and 1, and
DMATCR bit 4 (initial value)
Enables writing to all DMACR0B bits, DMABCR bits 9, 5, and 1, and
DMATCR bit 4.
0
1
Write enable 0A
Write enable 1B
Bit
DMAWER
Initial value
R/W
:
:
:
:
DMATCR—DMA Terminal Control Register H'FF61 DMAC
(This function is not available in the H8S/2695.)
7
—
0
—
6
—
0
—
5
TEE1
0
R/W
4
TEE0
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
Bit
DMATCR
Initial value
R/W
:
:
:
:
Disables TEND1 pin output.
Enables TEND1 pin output.
0
1
Transfer end pin enable 1
Disables TEND0 pin output.
Enables TEND0 pin output.
0
1
Transfer end pin enable 0