Datasheet

Appendix B Internal I/O Register
Page 1316 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit
DMACRB
Initial value
R/W
Full address mode
:
:
:
:
7
—
0
R/W
6
DAID
0
R/W
5
DAIDE
0
R/W
4
—
0
R/W
3
DTF3
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
Data Transfer Factor
DTF3 DTF2 DTF1 DTF0 Block Transfer Mode Normal Mode
— (initial value)
Activated by A/D converter
conversion end interrupt
Activated by DREQ pin falling edge
input
Activated by DREQ pin low-level input*
Activated by SCI channel 0
transmit-data-empty interrupt
Activated by SCI channel 0
reception complete interrupt
0
1
0
1
0
1
Activated by SCI channel 1
transmit-data-empty interrupt
0
Activated by SCI channel 1
reception complete interrupt
—
—
Activated by DREQ pin
falling edge input
Activated by DREQ pin
low-level input
—
—
Auto-request (cycle steal)
Auto-request (burst)1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
0
1
1
1
1
Activated by TPU channel 0 compare
match/input capture A interrupt
—
Activated by TPU channel 1 compare
match/input capture A interrupt
—
Activated by TPU channel 2 compare
match/input capture A interrupt
—
Activated by TPU channel 3 compare
match/input capture A interrupt
—
Activated by TPU channel 4 compare
match/input capture A interrupt
—
Activated by TPU channel 5 compare
match/input capture A interrupt
—
——
——
Destination Address Increment/Decrement
Note: * Detected as a low level in the first transfer after transfer is enabled.
0 MARB is fixed
1
0
1
0
1
MARB is incremented after a data transfer
• When DTSZ = 0, MARB is incremented by 1 after a transfer
• When DTSZ = 1, MARB is incremented by 2 after a transfer
MARB is fixed
MARB is decremented after a data transfer
• When DTSZ = 0, MARB is decremented by 1 after a transfer
• When DTSZ = 1, MARB is decremented by 2 after a transfer