Datasheet

Appendix B Internal I/O Register
Page 1318 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
DMABCR—DMA Band Control Register H'FF66 DMAC
(This function is not available in the H8S/2695.)
Short address mode
15
FAE1
0
R/W
14
FAE0
0
R/W
13
SAE1
0
R/W
12
SAE0
0
R/W
11
DTA1B
0
R/W
8
DTA0A
0
R/W
10
DTA1A
0
R/W
9
DTA0B
0
R/W
7
DTE1B
0
R/W
6
DTE1A
0
R/W
5
DTE0B
0
R/W
4
DTE0A
0
R/W
3
DTIE1B
0
R/W
0
DTIE0A
0
R/W
2
DTIE1A
0
R/W
1
DTIE0B
0
R/W
Full address enable 1
Data transfer acknowledge 0A
Short address mode.
Full address mode.
0
1
Transfer in dual address mode.
Transfer in single address mode.
0
1
Short address mode.
Full address mode.
0
1
Clearing of selected internal interrupt factor at DMA transfer disabled.
Clearing of selected internal interrupt factor at DMA transfer enabled.
0
1
Clearing of selected internal interrupt factor at DMA transfer disabled.
Clearing of selected internal interrupt factor at DMA transfer enabled.
0
1
Clearing of selected internal interrupt factor at DMA transfer disabled.
Clearing of selected internal interrupt factor at DMA transfer enabled.
0
1
Clearing of selected internal interrupt factor at DMA transfer disabled.
Clearing of selected internal interrupt factor at DMA transfer enabled.
0
1
Full address enable 0
Transfer in dual address mode.
Transfer in single address mode.
0
1
Single address enable 1
Single address enable 0
Data transfer acknowledge 0B
Data transfer acknowledge 1A
Data transfer acknowledge 1B
Data transfer enable 1B
Data transfer interrupt enable 0A
Data transfer disabled.
Data transfer enabled.
0
1
Data transfer disabled.
Data transfer enabled.
0
1
Data transfer disabled.
Data transfer enabled.
0
1
Transfer end interrupt disabled.
Transfer end interrupt enabled.
0
1
Transfer end interrupt disabled.
Transfer end interrupt enabled.
0
1
Transfer end interrupt disabled.
Transfer end interrupt enabled.
0
1
Transfer end interrupt disabled.
Transfer end interrupt enabled.
0
1
Data transfer enable 1A
Data transfer disabled.
Data transfer enabled.
0
1
Data transfer enable 0B
Data transfer enable 0A
Data transfer interrupt enable 0B
Data transfer interrupt enable 1A
Data transfer interrupt enable 1B
Bit
DMABCRH
Initial value
R/W
:
:
:
:
Bit
DMABCRL
Initial value
R/W
:
:
:
: