Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1323 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
ICCR0—I
2
C Bus Control Register
ICCR1—I
2
C Bus Control Register
H'FF78
H'FF80
IIC0
IIC1
(These functions are not available in the H8S/2695.)
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
0
R/W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
Bus busy
0 Bus is free
[Clearing condition]
When a stop condition is detected
1 Bus is free
[Setting condition]
When a stop condition is detected
I
2
C Bus interface interrupt request flag
0 Waiting for transfer, or transfer in progress
1 Interrupt requested
I
2
C Bus Interface Interrupt Enable
0 Interrupts disabled
1 Interrupts enabled
I
2
C Bus Interface Enable
0 I
2
C bus interface module disabled, with SCL and SDA signal pins set to port function
I
2
C bus interface module internal states initialized SAR and SARX can be accessed
1 I
2
C bus interface module enabled for transfer operations (pins SCL and SCA are driving
the bus)
ICMR and ICDR can be accessed
Acknowledge bit judgement selection
0 The value of the acknowledge bit is ignored, and
continuous transfer is performed
1 If the acknowledge bit is 1, continuous transfer is
interrupted
Start condition/stop condition prohibit
0 Writing 0 issues a start or stop condition,
in combination with the BBSY flag
1 Reading always returns a value of 1
Writing is ignored
Master/slave select, transmit/receive select
0 0 Slave receive mode
1 Slave transmit mode
1 0 Master receive mode
1 Master transmit mode
Note: * For details see section 18.2.5, I
2
C Bus
Control Register (ICCR).
Note: * For details see section 18.2.5, I
2
C Bus
Control Register (ICCR).
Note: * Only 0 can be written, for flag clearing.
Bit
Initial value
R/W
:
:
: