Datasheet

Section 2 CPU
Page 82 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
(a) Normal Mode
*
(b) Advanced Mode
Branch address
Specified
by @aa:8
Specified
by @aa:8
Reserved
Branch address
Note: * Not available in the H8S/2633 Group.
Figure 2.13 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
2.7.2 Effective Address Calculation
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal
mode
*
the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: * Not available in the H8S/2633 Group.