Datasheet

Appendix B Internal I/O Register
Page 1328 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
ADCSR—A/D Control/Status Register H'FF98 A/D
7
ADF
0
R/(W)*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CH3
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
Note: * Only 0 can be written to these bits (to clear these flags).
A/D end flag
0 [Clearing conditions]
(1) Writing 0 to the ADF flag after reading ADF=1.
(2) When DTC is started by an ADI interrupt and ADDR is read.
1 [Setting conditions]
(1) Single mode: On completion of A/D conversion.
(2) Scan mode: On completion of conversion of all specified channels.
A/D start
0 A/D conversion disabled.
1 (1) Single mode: A/D conversion starts. Automatically cleared
to 0 on completion of conversion on specified channel.
(2) Scan mode: A/D conversion starts. The selected channel
continues to be sequentially converted until this bit is
cleared to 0 by a software, reset, or standby mode is
selected, or module stop mode is selected.
A/D interrupt enable
0 A/D conversion end interrupt (ADI) requests disabled.
1 A/D conversion end interrupt (ADI) requests enabled.
Scan mode
0 Single mode
1 Scan mode
Channel select 3
0 AN8 to AN11 set as group 0 analog input
pins, and AN12 to AN15 as group 1
analog input pins.
1 AN0 to AN3 set as group 0 analog input
pins, and AN4 to AN7 set as group 1
analog input pins.
Channel select 2 to 0
CH3 CH2 CH1 CH0 Single mode Scan mode
(SCAN= 0) (SCAN= 1)
0 0 0 0 AN0 AN0
1 AN1 AN0, AN1
1 0 AN2 AN0 to AN2
1 AN3 AN0 to AN3
1 0 0 AN4 AN4
1 AN5 AN4, AN5
1 0 AN6 AN4 to AN6
1 AN7 AN4 to AN7
1 0 0 0 AN8 AN8
1 AN9 AN8, AN9
1 0 AN10 AN8 to AN10
1 AN11 AN8 to AN11
1 0 0 AN12 AN12
1 AN13 AN12, AN13
1 0 AN14 AN12 to AN14
1 AN15 AN12 to AN15
Bit
Initial value
R/W
:
:
: