Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1331 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
FLMCR1—Flash Memory Control Register 1 H'FFA8 FLASH
7
FWE
—*
R
6
SWE1
0
R/W
5
ESU1
0
R/W
4
PSU1
0
R/W
3
EV1
0
R/W
0
P1
0
R/W
2
PV1
0
R/W
1
E1
0
R/W
Flash write enable bit
Note: * Determined by the state of the FWE pin.
0 When LOW level signal input to FWE pin (hardware protect status).
1 When HIGH level signal input to FWE pin.
Software write enable bit 1
0 Writing disabled.
1 Writing enabled.
[Setting condition] When FWE=1.
Erase setup bit 1
0 Exits erase setup.
1 Erase setup.
[Setting condition] When FWE=1 and SWE1=1.
Program setup bit 1
0 Exits program setup.
1 Program setup.
[Setting condition] When FWE=1 and SWE1=1.
Erase verify 1
0 Exits erase verify mode.
1 Enters erase verify mode.
[Setting condition] When FWE=1 and SWE1=1
Program verify 1
0 Exits program verify mode.
1 Enters program verify mode.
[Setting condition] When FWE=1 and SWE1=1.
Erase 1
0 Exits erase mode.
1 Enters erase mode.
[Setting condition] When FWE=1, SWE1=1, and ESU1=1.
Program 1
0 Exits program mode.
1 Enters program mode.
[Setting condition] When FWE=1, SWE1=1, and PSU1=1.
Bit
Initial value
R/W
:
:
: