Datasheet

Appendix C I/O Port Block Diagrams
R01UH0166EJ0600 Rev. 6.00 Page 1337 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Appendix C I/O Port Block Diagrams
C.1 to C.12 are I/O port block diagrams for the H8S/2633, H8S/2632, H8S/2631, H8S/2633F, and
H8S/2633R. C.13 to C.24 are I/O port block diagrams for the H8S/2695.
C.1 Port 1 Block Diagram
R
P1nDDR
C
QD
Reset
Internal data bus
Internal address bus
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1n
*
RDR1
RPOR1
PPG module
DMA controller
TPU module
Pulse output enable
System controller
Address output enable
DMA transfer
acknowledge enable
Pulse output
DMA transfer acknowledge
Output compare output/
PWM output enable
Output compare output/
PWM output
Input capture input
WDDR1:
WDR1:
RDR1:
RPOR1:
n = 0 or 1
Note: *
Write to P1DDR
Write to P1DR
Read P1DR
Read port 1
Legend:
Priority order: Address output > Output compare output/PWM output > DMA transfer acknowledge output >
pulse output > DR output
Internal address bus
Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11)