Datasheet

Appendix C I/O Port Block Diagrams
Page 1338 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1n
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
System controller
Internal address bus
Address output enable
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
External clock input
Input capture input
*
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
n = 2 or 3
Note: * Priority order: address output > output compare output/PWM output > pulse output > DR output
Internal data bus Internal address bus
Figure C.1 (b) Port 1 Block Diagram (Pins P12 and P13)