Datasheet

Appendix C I/O Port Block Diagrams
Page 1340 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
P15DDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P15DR
C
QD
P15
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
Input capture input
External clock input
*
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Note: * Priority order: output compare output/PWM output > pulse output > DR output
Internal data bus
Figure C.1 (d) Port 1 Block Diagram (Pin P15)