Datasheet

Appendix C I/O Port Block Diagrams
R01UH0166EJ0600 Rev. 6.00 Page 1341 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
P16DDR
C
QD
Reset
WDDR1
Reset
Internal data bus
WDR1
R
P16DR
C
QD
P16
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
PWM module
PWM2 output enable
PWM2 output
Input capture input
Input controller
IRQ1 interrupt input
*
Legend
WDDR1:
WDR1:
RDR1:
RPOR1:
Write to P1DDR
Write to P1DR
Read P1DR
Read port 1
Note: * Priority order: output compare output/PWM output > PWM2 output > pulse output > DR output
Figure C.1 (e) Port 1 Block Diagram (Pin P16)