Datasheet

Appendix C I/O Port Block Diagrams
Page 1348 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
P35DDR
C
QD
Reset
Internal data bus
WDDR3
Reset
WDR3
R
C
QD
P35
RDR3
RODR3
RPOR3
SCI module
IIC0 module
SCL0 output
SCL0 input
IIC0 output enable
IRQ5 interrupt input
Interrupt controller
Serial clock output
enable
Serial clock output
Serial clock input
enable
P35DR
Reset
WODR3
R
C
QD
P35ODR
*
2
*
3
*
1
Serial clock input
Notes: 1. Priority order: IIC output > Serial clock output > DR output
2. Output enable signal
3. Open drain control signal
Legend:
WDDR3:
WDR3:
WODR3:
RDR3:
RPOR3:
RODR3:
Write to P3DDR
Write to P3DR
Write to P3ODR
Read P3DR
Read port 3
Read P3ODR
Figure C.2 (f) Port 3 Block Diagram (Pin P35)