Datasheet

Appendix C I/O Port Block Diagrams
Page 1352 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
C.4 Port 7 Block Diagram
R
P7nDDR
C
QD
Reset
Internal data bus
WDDR7
Mode 7
Modes 4 to 6
Reset
WDR7
R
P7nDR
C
QD
P7n
RDR7
RPOR7
DMA controller
Bus controller
Chip select
DMA request input
8-bit timer
Reset/Count input
WDDR7:
WDR7:
RDR7:
RPOR7:
n = 0 or 1
Write to P7DDR
Write to P7DR
Read P7DR
Read port 7
Legend:
Figure C.4 (a) Port 7 Block Diagram (Pins P70 and P71)