Datasheet

Appendix C I/O Port Block Diagrams
Page 1354 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
P73DDR
C
QD
Reset
Internal data bus
WDDR7
Mode 7
Modes 4 to 6
Reset
WDR7
R
P73DR
C
QD
P73
RDR7
RPOR7
Bus controller
Chip select
DMA controller
DMA transfer end enable
DMA transfer end
8-bit timer
Timer output TMO1
Timer output enable
*
WDDR7:
WDR7:
RDR7:
RPOR7:
Write to P7DDR
Write to P7DR
Read P7DR
Read port 7
Legend:
Note:
* Priority order: (Mode 7)
DMA transfer end output > 8-bit timer output > DR output
(Modes 4/5/6)
Chip select output > DMA transfer end output > 8-bit timer output > DR output
Figure C.4 (c) Port 7 Block Diagram (Pin P73)