Datasheet

Appendix C I/O Port Block Diagrams
Page 1364 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
C.7 Port B Block Diagram
R
PBnPCR
C
QD
Reset
Internal address bus
Internal data bus
WPCRB
Reset
WDRB
R
C
QD
PBn
RDRB
RODRB
RPORB
PBnDR
Reset
(Output compare)
TPU output
TPU output
enable
WDDRB
R
C
QD
PBnDDR
Reset
WODRB
RPCRB
R
C
QD
PBnODR
*
1
*
2
Modes 4 to 6
Address
enable
TPU input
(Input capture)
Notes: 1. Output enable signal
2. Open drain control signal
WDDRB:
WDRB:
WODRB:
WPCRB:
RDRB:
RPORB:
RODRB:
RPCRB:
n = 0 to 7
Write to PBDDR
Write to PBDR
Write to PBODR
Write to PBPCR
Read PBDR
Read port B
Read PBODR
Read PBPCR
Legend:
Figure C.7 Port B Block Diagram (Pins PB0 to PB7)