Datasheet

Section 2 CPU
R01UH0166EJ0600 Rev. 6.00 Page 87 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Exception handling state
Bus-released state
Hardware standby mode
*
2
Software standby mode
Power-on reset state
*
1
Sleep mode
Power-down state
*
3
Program execution state
End of bus request
Bus request
Interrupt request
External interrupt request
RES= High
Request for exception handling
STBY= High, RES= Low
End of bus
request
Bus request
SLEEP
instruction
with
SSBY = 0
SLEEP
instruction
with
SSBY =
1
Notes: 1.
2.
3.
From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES
goes low. From any state except hardware standby mode and power-on reset mode, a transition to the manual
reset state occurs whenever MRES goes low. A transition can also be made to the reset state when the
watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
Apart from these states, there are also the watch mode, subactive mode, and subsleep mode. (In the H8S/2695,
the watch mode, subactive mode, and subsleep mode are not available.) See section 24, Power-Down Modes.
E
n
d
o
f e
xce
p
tio
n
h
a
n
d
lin
g
Manual reset state
*
1
MRES= High
Reset state
*
1
Figure 2.15 State Transitions
2.8.2 Reset State
The CPU enters the reset state when the RES pin goes low, or when the MRES pin goes low while
manual resets are enabled by the MRESE bit. In the reset state, currently executing processing is
halted and all interrupts are disabled.
For details of MRESE bit setting, see section 3.2.2, System Control Register (SYSCR).
Reset exception handling starts when the RES or MRES pin
*
changes from low to high.
The reset state can also be entered in the event of watchdog timer overflow. For details see section
15, Watchdog Timer.
Note: * MRES pin in the case of a manual reset.