Datasheet

Appendix C I/O Port Block Diagrams
R01UH0166EJ0600 Rev. 6.00 Page 1381 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
C.13 Port 1 Block Diagram
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1n
*
RDR1
RPOR1
Internal data bus Internal address bus
System controller
*1
Address output enable
TPU module
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Input capture input
WDDR1:
WDR1:
RDR1:
RPOR1:
n = 0 or 1
Note: *
Write to P1DDR
Write to P1DR
Read P1DR
Read port 1
Legend:
Priority order:
1. Always disabled in mode 7.
Address output
*1
> Output compare output/PWM output > DR output
Figure C.13 (a) Port 1 Block Diagram (Pins P10 and P11)