Datasheet

Appendix C I/O Port Block Diagrams
Page 1388 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
P31DDR
C
QD
Reset
WDDR3
Reset
WDR3
R
C
QD
P31
RDR3
RODR3
RPOR3
P31DR
Reset
WODR3
R
C
QD
P31ODR
*
1
*
2
Notes: 1. Output enable signal
2. Open drain control signal
Legend:
WDDR3:
WDR3:
WODR3:
RDR3:
RPOR3:
RODR3:
Write to P3DDR
Write to P3DR
Write to P3ODR
Read P3DR
Read port 3
Read P3ODR
Internal data bus
SCI module
Serial receive data
enable
Serial receive data
RxD0/IrRxD
Figure C.14 (b) Port 3 Block Diagram (Pin P31)