Datasheet

Appendix C I/O Port Block Diagrams
Page 1392 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
C
QD
Reset
WDDR3
Reset
WDR3
R
C
QD
P35
RDR3
RODR3
RPOR3
Reset
WODR3
R
C
QD
*
2
*
3
*
1
Internal data bus
SCI module
IRQ5 interrupt input
Interrupt controller
Serial clock 1 output enable
Serial clock 4 output enable
Serial clock 1 output
Serial clock 4 output
Serial clock 1 input
Serial clock 4 input
Notes: 1. Priority order: Serial clock 4 output > DR output
2. Output enable signal
3. Open drain control signal
Legend:
WDDR3:
WDR3:
WODR3:
RDR3:
RPOR3:
RODR3:
Write to P3DDR
Write to P3DR
Write to P3ODR
Read P3DR
Read port 3
Read P3ODR
P35ODR
P35DR
P35DDR
Figure C.14 (f) Port 3 Block Diagram (Pin P35)