Datasheet

Appendix C I/O Port Block Diagrams
Page 1398 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
P75DDR
C
QD
Reset
WDDR7
Reset
WDR7
R
P75DR
C
QD
P75
RDR7
RPOR7
*
Internal data bus
SCI module
Serial clock output
enable
Serial clock input
enable
Serial clock
Serial clock input
WDDR7:
WDR7:
RDR7:
RPOR7:
Write to P7DDR
Write to P7DR
Read P7DR
Read port 7
Legend:
Note: * Priority order: Serial clock output > DR output
Figure C.16 (c) Port 7 Block Diagram (Pin P75)