Datasheet

Appendix C I/O Port Block Diagrams
Page 1402 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
C.18 Port A Block Diagram
R
PA0PCR
C
QD
Reset
WPCRA
Reset
WDRA
R
C
QD
PA0
RDRA
RODRA
RPORA
PA0DR
Reset
WDDRA
R
C
QD
PA0DDR
Reset
WODRA
RPCRA
R
C
QD
PA0ODR
*
1
*
2
Modes 4 to 6
Address
enable
Internal data bus Internal address bus
Notes: 1. Output enable signal
2. Open drain control signal
WDDRA:
WDRA:
WODRA:
WPCRA:
RDRA:
RPORA:
RODRA:
RPCRA:
Write to PADDR
Write to PADR
Write to PAODR
Write to PAPCR
Read PADR
Read port A
Read PAODR
Read PAPCR
Legend:
Figure C.18 (a) Port A Block Diagram (Pin PA0)