Datasheet

Appendix C I/O Port Block Diagrams
R01UH0166EJ0600 Rev. 6.00 Page 1403 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
PA1PCR
C
QD
Reset
WPCRA
Reset
WDRA
R
C
QD
PA1
RDRA
RODRA
RPORA
PA1DR
Reset
WDDRA
R
C
QD
PA1DDR
Reset
WODRA
RPCRA
R
C
QD
PA1ODR
*
1
*
2
Modes 4 to 6
Address
enable
Smart card
mode signal
TxD output
TxD output
enable
Internal address bus Internal data bus
Notes: 1. Output enable signal
2. Open drain control signal
WDDRA:
WDRA:
WODRA:
WPCRA:
RDRA:
RPORA:
RODRA:
RPCRA:
Write to PADDR
Write to PADR
Write to PAODR
Write to PAPCR
Read PADR
Read port A
Read PAODR
Read PAPCR
Legend:
Figure C.18 (b) Port A Block Diagram (Pin PA1)