Datasheet

Appendix C I/O Port Block Diagrams
R01UH0166EJ0600 Rev. 6.00 Page 1405 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
R
PA3PCR
C
QD
Reset
WPCRA
Reset
WDRA
R
C
QD
PA3
RDRA
RODRA
RPORA
PA3DR
Reset
SCK input
WDDRA
R
C
QD
PA3DDR
Reset
WODRA
RPCRA
R
C
QD
PA3ODR
*
1
*
2
Internal data bus Internal address bus
SCK input
enable
SCK output
SCK output
enable
Modes 4 to 6
Address
enable
Notes: 1. Output enable signal
2. Open drain control signal
WDDRA:
WDRA:
WODRA:
WPCRA:
RDRA:
RPORA:
RODRA:
RPCRA:
Write to PADDR
Write to PADR
Write to PAODR
Write to PAPCR
Read PADR
Read port A
Read PAODR
Read PAPCR
Legend:
Figure C.18 (d) Port A Block Diagram (Pin PA3)