Datasheet

Appendix D Pin States
R01UH0166EJ0600 Rev. 6.00 Page 1425 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Port Name
Pin Name
MCU
Operating
Mode
Power-
On
Reset
Manual
Reset
Hardware
Standby
Mode
Software
Standby
Mode
Bus
Release
State
Program
Execution
State
Sleep Mode
PG3/CS1
PG2/CS2
4 to 6 T kept T [DDR = 1,
OPE = 0]
T
[DDR = 1,
OPE = 1]
H
[DDR = 0]
T
T [DDR = 0]
Input port
[DDR = 1]
CS2 to CS1
7 T kept T kept kept I/O port
PG1/CS3/
OE/IRQ7
4 to 6 T kept T [DDR = 1,
OPE = 0]
T
[DDR = 1,
OPE = 1]
H
[DDR = 0]
T
T [DDR = 0]
Input port
[OE = 0,
DDR = 1]
CS3
[OE = 1,
DDR = 1]
OE
7 T kept T kept kept I/O port
PG0/CAS/
IRQ6
4 to 6 T kept T [DRAME = 0]
kept
[DRAME = 1,
OPE = 1]
CAS
[DRAME = 1,
OPE = 1]
T
T [DRAME = 0]
I/O port
[DRAME = 1]
CAS
7 T kept T kept kept I/O port
Legend:
H: High level
L: Low level
T: High impedance
kept: Input port becomes high-impedance, output port retains state
DDR: Data direction register
OPE: Output port enable
WAITE: Wait input enable
BRLE: Bus release enable
BREQOE: BREQO pin enable
DRAME: DRAM space setting
LCASE: DRAM space setting, CW2 = LCASS = 0
Note: * Indicates the state after completion of the executing bus cycle.