Datasheet

Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Page 1430 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at
least 10 states before the STBY signal goes low, as shown below. RES must remain low until
STBY signal goes low (delay from STBY low to RES high: 0 ns or more).
STBY
RES
t
2
≥ 0 ns
t
1
≥ 10 t
cyc
Figure E.1 Timing of Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents
do not need to be retained, RES does not have to be driven low as in (1).
Timing of Recovery from Hardware Standby Mode
Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY
goes high to execute a power-on reset.
t
OSC
t
NMIRH
t ≥ 100 ns
NMI
STBY
RES
Figure E.2 Timing of Recovery from Hardware Standby Mode