Datasheet

Section 2 CPU
R01UH0166EJ0600 Rev. 6.00 Page 93 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bus cycle
T1
UnchangedAddress bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High-impedance state
Figure 2.18 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the
access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.