Datasheet

Section 2 CPU
Page 94 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bus cycle
T1 T2
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Internal address bus
φ
Figure 2.19 On-Chip Supporting Module Access Cycle
Bus cycle
T1 T2
Unchanged
Address bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High-impedance state
Figure 2.20 Pin States during On-Chip Supporting Module Access