Datasheet

Section 2 CPU

R01UH0166EJ0600 Rev. 6.00 Page 95 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

2.9.4 External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or

three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to

section 7, Bus Controller.

2.10 Usage Note

2.10.1 TAS Instruction

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS

instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. If the TAS

instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or

ER5 is used.

2.10.2 STM/LDM Instruction

With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot

be used as a register that allows save (STM) or restore (LDM) operation.

With a single STM or LDM instruction, two to four registers can be saved or restored. The

available registers are as follows:

For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5

For three registers: ER0 to ER2, or ER4 to ER6

For four registers: ER0 to ER3

For the Renesas H8S or H8/300 Series C/C++ Compiler, the STM/LDM instruction including ER7

is not created.

2.10.3 Usage Notes on Bit Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate

the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore,

special care is necessary to use these instructions for the registers and the ports that include write-

only bit.

The BCLR instruction can be used to clear to 0 the flags in the internal I/O registers. In this time,

if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the

flag beforehand.