Datasheet

Section 3 MCU Operating Modes
R01UH0166EJ0600 Rev. 6.00 Page 99 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
levels are latched into these bits when MDCR is read. These latches are cancelled by a power-on
reset, but maintained by a manual reset.
3.2.2 System Control Register (SYSCR)
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
MRESE
0
R/W
1
—
0
—
Bit
Initial value
R/W
:
:
:
SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI,
enables or disables MRES pin input, and enables or disables on-chip RAM.
SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. MACS, INTM1,
INTM0, NMIEG, and RAME bits are initialized in manual reset mode, but the MRESE bit is not
initialized. SYSCR is not initialized in software standby mode.
Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the
MAC instruction.
Bit 7
MACS Description
0 Non-saturating calculation for MAC instruction (Initial value)
1 Saturating calculation for MAC instruction
Bit 6—Reserved: This bit always read as 0 and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5 Bit 4
INTM1 INTM0
Interrupt
Control Mode Description
0 0 0 Control of interrupts by I bit (Initial value)
1 — Setting prohibited
1 0 2 Control of interrupts by I2 to I0 bits and IPR
1 — Setting prohibited