Datasheet

Section 3 MCU Operating Modes
Page 100 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG Description
0 An interrupt is requested at the falling edge of NMI input (Initial value)
1 An interrupt is requested at the rising edge of NMI input
Bit 2—Manual Reset Selection Bit (MRESE): Enables or disables manual reset input. It is
possible to set the P74/TM02/MRES pin to the manual reset input (MRES).
Table 3.3 shows the relationship between the MRES pin power-on reset and manual reset.
Bit 2
MRESE Description
0 Disables manual reset.
Possible to use P74/TM02
*
/MRES pin as P74/TM02
*
input pin. (Initial value)
1 Enables manual reset.
Possible to use P74/TM02
*
/MRES pin as MRES input pin.
Note: * This function is not available in the H8S/2695.
Table 3.3 Relationship Between Power-On Reset and Manual Reset
Pin
RES MRES Reset Type
0 * Power-on reset (Initial state)
1 0 Manual reset
1 1 Operation state
*: Don't care
Bit 1—Reserved: This bit always read as 0 and cannot be modified.