Datasheet

Section 3 MCU Operating Modes
R01UH0166EJ0600 Rev. 6.00 Page 101 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
Notes: When the DTC
*
is used, the RAME bit must be set to 1.
* The DTC function is not available in the H8S/2695.
3.2.3 Pin Function Control Register (PFCR)
7
CSS07
0
R/W
6
CSS36
0
R/W
5
BUZZE
0
R/W
4
LCASS
0
R/W
3
AE3
1/0
R/W
0
AE0
1/0
R/W
2
AE2
1/0
R/W
1
AE1
0
R/W
Bit
Initial value
R/W
:
:
:
PFCR is an 8-bit readable-writable register that carries out CS selection control for PG4 and PG1
pins, LCAS selection control for PF2 and PF6 pins, and address output control during extension
modes with ROM.
PFCR is initialized by H'0D/H'00 by a power-on reset or a hardware standby mode. The
immediately previous state is maintained in manual reset or software standby mode.
Bit 7—CS0/CS7 Select (CSS07): Selects the CS output content for PG4 pin. In modes 4 to 6, the
selected CS is output by setting the corresponding DDR to 1.
Bit 7
CSS07 Description
0 Select CS0 (Initial value)
1 Select CS7