Datasheet

Section 3 MCU Operating Modes
Page 102 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 6—CS3/CS6 Select (CSS36): Selects the CS output content for PG1 pin. In modes 4 to 6, the
selected CS is output by setting the corresponding DDR to 1.
Bit 6
CSS36 Description
0 Select CS3 (Initial value)
1 Select CS6
Bit 5—BUZZ Output Enable (BUZZE)
*
: Disables/enables BUZZ output of PF1 pin. Input
clock of WDT1 selected by PSS, CKS2 to CKS0 bits is output as a BUZZ signal.
Bit 5
BUZZE Description
0 Functions as PF1 input pin (Initial value)
1 Functions as BUZZ output pin
Note: * This function is not available in the H8S/2695. This bit should not be set to 1.
Bit 4—LCAS Output Pin Selection Bit (LCASS)
*
: Selects the LCAS signal output pin.
Bit 4
LCASS Description
0 Outputs LCAS signal from PF2 (Initial value)
1 Outputs LCAS signal from PF6
Note: * This function is not available in the H8S/2695. This bit should not be set to 1.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling
of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is
enabled for address output, the address is output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an output port when the corresponding DDR
bit is set to 1.